1. Field of the Invention
This invention relates to the method of implementing an automatic routing layout for automated universal arrays and more particularly to a computer program which effectively routes conductors on both levels of a double level metal automated universal array.
2. Description of the Prior Art
Large scale integrated semiconductor arrays comprising a layout of predefined uncommitted semiconductor devices are generally well known and comprise an orderly uniform arrangement of standard basic units of semiconductor devices selectively interconnected to form a combination of "logic cells" or gates which are further interconnected to provide a customized integrated circuit. A universal array particularly adapted for automatic layout techniques is shown and disclosed, for example, in applicant's copending application entitled, "Automated Universal Array", U.S. Ser. No. 305,825, which was filed in the name of F. Borgini, et al. on Sept. 28, 1981. There the array comprises an interior row region of many parallel rows of identical basic units. Each basic unit, moreover, contains four semiconductor devices with one or more basic units being further utilized upon being connected for implementing a logic cell such as an AND gate, OR gate, flip-flop, etc. This interior region is surrounded by a rectangular annular region of peripheral devices and contact pads for the connection of external leads thereto. The rows of basic units are, moreover, spaced apart by wiring roadbeds which together with a defined pattern of tunnels provide a means whereby suitable interconnection to the various devices can be made. Another similar type of universal array is disclosed in U.S. Ser. No. 562,245, entitled, "Improved Circuit Density ICs", filed in the name of R. Pryor on Dec. 16, 1983.
In implementing the interconnects, a customizing conductive layer is first applied over the array surface and thereafter coated with photoresist material and then exposed to activating radiation through a custom patterned mask. The custom masked pattern causes the activating radiation to protect those portions of the conductive material which are needed to interconnect the semiconductor devices while leaving unprotected the remaining portions of the customizing conductive layer. The unprotected portions of the customizing layer are removed by etching and the resulting structure is thereafter passivated to prevent environmental damage.
Because hand design of a customizing mask for this type of array has been found to be prohibitively time consuming and expensive, computer aided design (CAD) systems have been developed to automatically design the customizing mask. Such systems accept an input of a desired integrated circuit design and thereafter generate a specification of a mask pattern which is used to pattern the conductive layer into the desired integrated circuit structure. This is done through a computer implemented process involving automatic assignment of logic cells to rows of the universal array, automatic placement of assigned logic cells along the rows, and automatic routing of customizing conductors or wires. The resulting mask specification is then used to control a mask generating computer system which converts the specification into the physical pattern of the mask. Thereafter, that mask is used in a photoetcher to customize the specific circuit configuration.
A computer aided design system must insure that 100% of the customizing conductors are routed automatically in order for its mask specification to be directly convertible to the final mask used to pattern the customizing layer. Semiconductor area is wasted if a routing system must restrict an integrated circuit design to actually using only a relatively low percentage, typically 60% or 70% of the universal array's basic units. Some placement and routing systems must impose such restrictions in order to insure the routing system's ability to complete routing of 100% of the connecting conductors. It is therefore desirable that the automatic system be able to complete 100% of the routing and circuits which use high percentages of the basis units which are available in the array.
Two improved methods of cell placement and conductor routing on a single level of metallization are known and are disclosed, for example, in two pending applications. Respectively they comprise a patent application entitled, "Cell Placement Method in Computer-Aided-Customization of Universal Arrays and Resulting Integrated Circuit", by Richard Noto and David C. Smith, U.S. Ser. No. 608,788, filed on May 10, 1984, and a patent application entitled, "Routing Method in Computer-Aided-Customization of Universal Arrays and Resulting Integrated Circuit", by David C. Smith and Richard Noto, Ser. No. 608 772, filed on May 10 1984. The teachings of these applications are meant to be specifically incorporated herein by reference.
The routing process disclosed in the aforementioned application Ser. No. 608,772 involves an iteration of direct routing and pathfinding routing routines. In direct routing, the process checks each route in a specific-limited set of possible routes to see if one of these routes is available for the conductor being routed and follows straight line segments which extend parallel to or perpendicular to the roadbed intermediate the rows of basic units. The direct router selects the first one of those routes which is available as the route that conductor will take. If none of those routes is available, a pathfinding routing technique is resorted to.
In the cell placement method disclosed, unused basic units are assigned to rows in an inverse barrel configuration to reduce the congestion of the wiring in high congested regions of a universal array and is particularly applicable to a variable geometry array such as disclosed in a patent application entitled, "Variable Geometry Automated Universal Array", U.S. Ser. No. 474,511, now U.S. Pat. No. 4,568,961, which was filed in the name of Richard Noto, on Mar. 11, 1983.
Conductor routing on a plurality of different levels is also known. An example of this technique is disclosed in U.S. Pat. No. 4,500,963, entitled, "Automatic Layout Program For Hybrid Microcircuits (Hypar)", which issued to David C. Smith, et al. on Feb. 19, 1985. The teachings of this patent are also meant to be incorporated herein by reference.
Accordingly, it is an object of the present invention to provide an improvement in automatic layout programs for automated universal arrays.
It is a further object of the invention to provide an improvement in the routing of conductors in computer aided customization of automated universal arrays.
Still a further object of the invention is to provide an improved routing method in the computer aided customization of a two level automated universal array.